Integrated circuit (IC) devices may be provided with high voltage protection circuits to protect the devices from the high voltages caused by electrostatic charges, which may be potentially damaging. These high voltage protection circuits have utilized SCRs that generally trigger in response to high voltages at the ICs I/O pads or pins to provide a path for dissipating the voltage away from the device being protected. Examples of the use of SCRs in protection circuits are shown in U.S. Pat. Nos. 5,567,500, 4,072,273, and 4,870,530.
One problem of these SCR-based protection circuits is that after a high ESD voltage triggers the SCR to turn on, it is difficult to turn it off again (i.e., unlatch) because very low currents (for example, &lt;10 mA) at the gates of the SCR will usually keep the SCR on. The standard solutions to this problem are to either completely remove the input signal or to remove the power to the device being protected. Both of these solutions are impractical in operating systems. This is especially a problem in situations where the circuits are used is very remote systems, such as an orbiting satellite. Therefore, it is desirable to automatically turn off the SCR once the high voltage ESD pulse has been removed and the voltage at the pin connected to the protection circuit has returned to a normal operating voltage range.
Another problem with SCR-based protection circuits is that they generally do not provide ESD protection when the IC device it is protecting is not powered up. It is thus further desirable to provide a protection circuit that will not only protect an IC device when the device is powered but also when the IC device is not powered.